With a continuous development of CMOS (Complementary Metal Oxide Semiconductor) process, it becomes harder to scale down the size of the chip. Thus, more and more designers begin to focus on a multi-chip package, rather than continue relying on integrating more devices on a single chip, so as to improve a performance of the chip. Stacked chip packaging technology (a three-dimensional package for short) refers to a packaging technology that stacks two or more chips in a vertical direction in the same package body without changing a size of the package body. Due to a connection of TSVs (Through Si via) between layers, the three-dimensional integrated circuit can effectively solve the delay problem of the two-dimensional integrated circuit.
The three-dimensional package can significantly reduce the size of the chip, increase a transistor density of the chip, improve the electrical interconnection performance between layers, enhance a running speed of the chip, and reduce the power consumption and the delay of the chip to a great extent. By introducing the concept of the three-dimensional integrated circuit in the design stage, a complete and complex chip can be divided into several sub-chips which are realized in different layers. Thus, a function of the chip is enhanced, and a lot of problems such as high cost and design complexity are avoided. In addition, the use of the three-dimensional package may also reduce the power consumption.
However, the three-dimensional chip design and manufacture processes are complex, in which the test and heat problem are two difficult problems. On one hand, as the three-dimensional chips need to be tested before being bound, the test problem of the three-dimensional chip must be solved. On the other hand, due to the high interconnection density, the heat problem of the three-dimensional chip becomes much worse. Furthermore, with a further development of COMS process, the power density in the microelectronic design becomes much greater. For example, the power density of a high-performance microprocessor with a size of 10 nm has reached 50 W/cm2, and when the size of the high-performance microprocessor is less than 50 nm, the power density thereof will quickly increases to 100 W/cm2. The power density increment of the microprocessor will lead to a rapid increment of the temperature of the chip. Further, the power density of a hotspot on the chip is usually much higher than that of other places, so that the temperature of the hotspot is much higher than that of other places. As the energy consumed by the microprocessor is converted into heat energy, the corresponding heat density presents an exponential growth, thus leading to a sharp decreasing of the reliability and a significant rising of a manufacture cost.
At any power dissipation level, the generated heat must be removed rapidly from the surface of the chip. However, the existing cooling method is expensive. Especially for the high-performance microprocessor, cooling cost is quite high, which is a threat for the computer industry to deploy new systems.